Ohmforge Microcontroller Timing Calculator
UART baud error (UBRR, BRR), timer prescalers, PWM resolution, ADC LSB/ENOB and RC delays.
Try an example: ATmega328P at 16 MHz: 115200 baud · STM32 at 8 MHz: 9600 baud with 8× oversampling (RM0360 example) · AVR Timer1: 1 kHz interrupt from 16 MHz · STM32 timer: 1 Hz from 72 MHz · Arduino pin PWM: 490 Hz phase-correct, 8 bit · 12-bit ADC at 3.3 V with 70 dB SINAD · Reset RC: 10 kΩ and 100 nF into a 5 V Schmitt input
How it works
Five firmware calculations with exact integer arithmetic: the UART divider (AVR UBRR normal and double speed, STM32 BRR with 16× or 8× oversampling, or any divider) with the real baud rate and error for your clock, a timer solver that finds prescaler and compare value for a target frequency or period on 8-, 16- or 32-bit timers, PWM frequency against resolution for fast and phase-correct PWM, ADC LSB size, ideal SNR and ENOB from SINAD, and RC reset or debounce times to a logic threshold.
- UART: AVR UBRR = round(fOSC/(16·baud) − 1) (U2X = 1: /8), real baud = fOSC/(16·(UBRR + 1)); STM32 USARTDIV = round(fCK/baud) with 16× oversampling and round(2·fCK/baud) with 8× oversampling, where BRR keeps USARTDIV[15:4] and BRR[2:0] = USARTDIV[3:0] >> 1 (USARTDIV ≥ 16); generic divider D = round(f/(N·baud)·2^F)/2^F. Error = real/wanted − 1.
- Timer: f = fCLK/(P·N) with prescaler P and N counts per period (compare/auto-reload value N − 1). For each prescaler N = round(fCLK/(P·f)) must fit the timer (1 … 2^bits). "Any 1 … 65536" searches every prescaler and keeps the 10 best by error, then by most counts (finest resolution).
- PWM: fast (single-slope) PWM f = fCLK/(P·(TOP + 1)); phase-correct (dual-slope) PWM f = fCLK/(2·P·TOP). In both modes the compare value runs 0 … TOP, so the resolution is log2(TOP + 1) bits.
- ADC: LSB = Vref/2^N (the convention of most datasheets: code = floor(Vin·2^N/Vref)), quantisation noise LSB/√12, ideal SNR = 6.02·N + 1.76 dB for a full-scale sine, ENOB = (SINAD − 1.76)/6.02.
- RC: the capacitor charges through R from 0 V: t = −RC·ln(1 − Vth/V) to the high threshold; discharging from V: t = −RC·ln(Vth/V) to the low threshold; settling to 1 % takes RC·ln 100 ≈ 4.6 RC.
Register names and formulas follow the cited families; other microcontrollers differ (extra prescaler stages, fractional dividers, clock trees). Check the reference manual of your exact part. The RC result assumes ideal parts and a high-impedance input; real thresholds vary with supply and temperature.
Sources
- Microchip: ATmega48A/PA/88A/PA/168A/PA/328/P datasheet — USART baud rate generation and examples of UBRR settings (Microchip Technology)
- STMicroelectronics RM0360: STM32F030/F070 reference manual — USART baud rate generation (STMicroelectronics)
- Analog Devices MT-001: Taking the Mystery out of the Infamous Formula "SNR = 6.02N + 1.76 dB" (Analog Devices)
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Calculate UART baud error, timer prescalers, PWM, ADC and RC delays
Find the UBRR or BRR value and the real baud rate, the prescaler and compare value for a timer, PWM resolution, ADC LSB and ENOB, and RC switching times.
What it is for
Firmware bugs that look mysterious are often plain arithmetic: a serial port that drops characters because the baud rate is 3.5 % off, a timer that drifts because the prescaler does not divide evenly, a PWM that is audible because its resolution forced a low frequency. This calculator does that arithmetic exactly for the clock you really have.
Pick a Calculation:
- UART baud rate computes the AVR UBRR (normal and double speed) or the STM32 BRR (16× or 8× oversampling), or a generic divider. You get the real baud rate, the error and a table of common rates.
- Timer prescaler and period finds the prescaler and compare value for a target frequency or period on 8-, 16- or 32-bit timers.
- PWM frequency and resolution shows what TOP and resolution each prescaler gives, in fast or phase-correct mode.
- ADC resolution and ENOB gives the LSB, the ideal SNR and the effective number of bits from a datasheet SINAD.
- RC reset or debounce time calculates when a capacitor charging through a resistor crosses a logic threshold.
Formulas follow the ATmega328P datasheet and STM32 reference manuals. Other chips can have extra prescalers or fractional dividers, so check your reference manual.
Worked example
An ATmega328P running from its 8 MHz internal oscillator should talk at 57600 baud. In normal mode UBRR = 8 gives 55555.56 baud, an error of −3.55 %, outside the usual ±2 % limit. The callout points to double speed: with U2X = 1, UBRR = 16 gives 58823.53 baud, +2.12 %, still slightly too far off. The common-rates table shows that 38400 baud (UBRR 12, +0.16 %) is a safe choice at this clock.
For a 50 Hz servo frame on an STM32 timer clocked at 48 MHz, choose Any 1 … 65536. The best pair is prescaler 15 with compare value 63999 (64000 counts), exactly 50 Hz. In the registers that is PSC = 14 and ARR = 63999.
A 20 kHz motor PWM from 16 MHz uses prescaler 1 with TOP = 799: 800 steps, 9.644 bits of resolution.
How to read the result
The headline metrics show the register value to program and the real result. Error is real ÷ wanted − 1. In the timer table, Counts N is the number of timer ticks per period; the compare or auto-reload register holds N − 1. In PWM mode, Frequency for a fixed resolution answers the reverse question: what frequency do 8 or 10 bits give with each prescaler?
Tips and common mistakes
- Both ends of a serial link have their own error. Keep each below ±2 %, or use a "baud-rate crystal" such as 14.7456 MHz.
- Enter the clock that actually feeds the peripheral (APB or timer clock), not the CPU clock, if they differ.
- An internal RC oscillator can be off by a few percent on its own. Calibrate it before you trust 115200 baud.
- Some ADC datasheets define the LSB as Vref/(2^N − 1); the tool uses Vref/2^N like most.
- For RC reset circuits, add a diode across R so the capacitor discharges quickly when power drops.
FAQ
Why is 115200 baud unreliable on a 16 MHz Arduino?
UBRR 8 gives 111111 baud, −3.5 % in normal mode. Double speed (UBRR 16) brings it to +2.1 %, which usually works with an accurate partner.
What does ENOB mean?
The effective number of bits: the resolution of an ideal ADC with the same SINAD as yours. 70 dB SINAD equals 11.34 bits.
Is the timer solution with the most counts always best?
Among exact solutions it gives the finest PWM duty resolution and the smallest rounding when you change the period.
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-d '{"mode":"uart","clockMHz":16,"baud":115200,"uartMode":"avr","maxErrorPercent":2}'